1. Field of the Invention
The present invention relates generally to synchronous memory systems, and more particularly to synchronizing write data on a high speed memory bus.
2. Description of the Related Art
An exemplary computer system 1 is illustrated in FIG. 1. The computer system 1 includes a processor 401, a memory system 2, and a expansion bus controller 402. The memory system 2 and the expansion bus controller 402 are coupled to the processor 401 via a local bus 400. The expansion bus controller 402 is also coupled to one or more expansion buses 403, to which various peripheral devices such as mass storage devices, keyboard, mouse, graphics adapters, and multimedia adapters may be attached.
The memory system 2 includes a memory controller 100 which is connected to a plurality of memory modules 200 and 300 via a memory bus 106. The memory bus comprises a plurality of signal lines 101-105, which respectively communicate data DATA (over a plurality of lines 101), a data strobe STROBE, a write clock WCLK, a command clock CCLK, and commands and data CMD/DATA (over a plurality of lines 105). The memory modules 200 and 300 accept commands from the memory controller 100 synchronized on the rising edge of the command clock CCLK on signal line 104. A short time after the memory modules 200 and 300 accept a write command, the memory modules 200 and 300 accept write data synchronized on the rising and falling edges of the write clock WCLK. The number of write clock cycles which elapses between the synchronous semiconductor memory device accepting a write command and the time the synchronous semiconductor memory device begins accepting write data is known as write latency. During system initialization the memory controller and the memory modules are initialized to operate the memory system 2 with a desired write latency.
Each memory module 200 contains a register 201 and, in the example shown, a plurality of synchronous semiconductor memory devices 202-205. The timing diagram for a write operation to one of the synchronous semiconductor memory devices 202-205 is illustrated in FIG. 4. The write clock WCLK operates at double the frequency of the command clock CCLK. Both clocks are synchronized, so at the beginning of a clock cycle N of the command clock CCLK the write clock WCLK is beginning a corresponding 2N clock cycle. In FIG. 4, the exemplary memory is being operated with a write latency WL equal to 1 write clock cycle. Thus, when the write command is asserted on the command bus CMD on clock cycle T1, the system waits to satisfy the write latency WL requirement on clock cycle T2, and begins to accept write data on clock cycle T3. The synchronous semiconductor memory device operates in what is known as a burst mode, so it continues to accept write data over the next several clock cycles. In the illustrated example, the synchronous semiconductor memory device accepts an 8-length burst over 4 clock cycles T3-T6. Thus, if the command and write clocks are phase synchronized the synchronous semiconductor memory can count the number of write clock cycles which elapses after the device accepts a write command (synchronized with the command clock) to determine when it should being accepting write data.
However, the command and write clocks may not be synchronized. Referring now to FIG. 2, a more detailed diagram of the memory module 200 from FIG. 1 is shown. The memory module 200 features a register 201 which is used to buffer the command clock CCLK and commands and addresses CMD/ADDR. The buffered command clock CCLK and commands and addresses CMD/ADDR are then distributed to each of the synchronous semiconductor memory devices 202-205 on internal signal lines 104xe2x80x2 and 105xe2x80x2 respectively. On the other hand, each of the synchronous semiconductor memory devices 202-205 have their data signal line 101, strobe signal line 102, and write clock signal line 103 directly coupled to the memory bus 106. Since the command clock CCLK signal is delayed by being buffered via register 201 while the write clock WCLK is directly coupled to the semiconductor memory devices 202-205, an arbitrary phase shift exists between the write and command clocks. For example, FIGS. 5A and 5B are timing diagrams for a write operation with a 1 write clock write latency WL. In FIGS. 5A and 5B the write and command clock wave forms appear identical. However, in FIG. 5A, the phase shift PS is 1.5 write clocks, therefore the synchronous semiconductor memory device should satisfy the write latency WL requirement on clock T2 and accept data on clocks T3-T6, while in FIG. 5B the phase shift PS is 0.5 write clocks, therefore the synchronous semiconductor memory device should satisfy the write latency WL requirement on clock T1 and accept write data on clocks T2-T5. Since the phase shift is induced by a device external to a synchronous semiconductor memory device, it is impossible for the synchronous semiconductor memory device to accurately determine the proper cycle of the write clock WCLK upon which to begin accepting write data.
Accordingly, there is a need for an apparatus and method to synchronize write data in memory systems employing separate command and write clocks which may incur a phase shift.
The present invention is directed at a method and apparatus for synchronizing write data in a synchronous semiconductor memory device and system which supports separate write and command clocks. The present invention permits the synchronous semiconductor memory device to accurately determine upon which write clock cycle it begins to accept write data, even if there is an arbitrary phase shift between the command and write clocks. The present invention takes advantage of the unbuffered data strobe signal which is normally unused during a write operation. The memory controller of the present invention transmits a write flag on the data strobe signal line on the write clock cycle upon which the synchronous semiconductor memory device should begin accepting write data. The synchronous semiconductor memory device of the present invention detects the write flag transmitted by the memory controller and begins accepting write data when it detects the write flag.